1. Field of the Invention
The present invention relates to methods apparatus for receiving data, and, more particularly, to methods of receiving a current mode signal, which can improve a signal to noise ratio (SNR) according to a change in a power supply voltage, and current mode comparators and semiconductor devices that use the methods.
2. Description of the Related Art
In general, semiconductor devices receive and transmit data in the form of a voltage signal or a current signal with other semiconductor devices. Typically, the current signal is more effective in high-speed operation than the voltage signal.
Semiconductor devices receiving data in the form of a current signal may require a current mode receiving circuit that receives a current signal and extracts data. Current mode comparator circuits may be used as current mode receiving circuits. Current mode comparator circuits are data detection circuits that determine a logic state of data based on a difference between a received data current signal and a predetermined reference current signal.
FIG. 1 is a circuit diagram of a conventional current mode receiving circuit. Referring to FIG. 1, the conventional current mode receiving circuit includes a receiver 110 and a comparator 120. Information corresponding to a difference between an input data current signal Idata and a reference current signal Iref is represented as a change in a voltage V1 of a first node NO1. The change in the voltage V1 of the first node NO1 is converged into a CMOS level voltage signal RxData by two NAND gates ND1 and ND2 of the comparator 120. The comparator 120 is called a current to voltage converter because the comparator 120 converts the received data current signal Idata into the voltage signal RxData.
Two transistors MN and MP of the comparator 120 are used to limit the voltage V1 of the first node NO1. The two transistors MN and MP operate in a saturation region, and only one of the two transistors MN and MP operates according to the relative levels of the input data current signal Idata and the reference current signal Iref.
If the input data current signal Idata is lower than the reference current signal Iref, the voltage V1 of the first node NO1 is higher than a predetermined voltage, for example, VDD/2, and a voltage V2 of a second node NO2 is at a low level and the output data RxData is at a high level. At this time, the NMOS transistor MN is turned off and the PMOS transistor MP is turned on, such that a current In (In=Iref−Idata) corresponding to a difference between the reference current signal Iref and the data current signal (Idata) flows to a ground terminal through the PMOS transistor MP. The NMOS transistor MN is turned off, and, thus, the voltage V1 of the first node NO1 is stabilized.
On the other hand, if the input data current signal Idata is higher than the reference current signal Iref, the voltage V1 of the first node NO1 is lower than the predetermined voltage, for example, VDD/2, and the voltage V2 of the second node NO2 is at a high level and the output data RxData is at a low level. At this time, the NMOS transistor MN is turned on and the PMOS transistor MP is turned off, such that a current In (In=Idata−Iref) corresponding to a difference between the reference current signal Iref and the data current signal Idata is supplied to the first node NO1 through the NMOS transistor MN. The PMOS transistor MP is turned off, and, thus, the voltage V1 of the first node NO1 is stabilized.
When a power supply voltage VDD increases, a swing level of the voltage V2 of the second node NO2 increases. Accordingly, transconductances Gm of the NMOS transistor MN and the PMOS transistor MP increase, and, thus, an input resistance R2 of the comparator 120 decreases. The decrease in the input resistance R2 results in a decrease in a swing level of the voltage V1 of the first node NO1. FIG. 2 is a graph illustrating a relationship between the power supply voltage VDD and the swing level of the voltage V1 of the first node NO1 and the swing level of the voltage V2 of the second node NO2. When the power supply voltage VDD increases, a noise level may increase too.
FIG. 3 illustrates that an undesired operation may occur when the reference current signal Iref is relatively low and the power supply voltage VDD increases in the conventional current mode receiving circuit. Referring to FIG. 3, when the reference current signal Iref is set to 200 uA and the power supply voltage VDD increases, an undesired operation occurs. When the reference current signal Iref increases, undesirable operations are reduced, but power consumption increases.
Accordingly, the conventional current mode receiving circuit has disadvantages in that, when the power supply voltage VDD increases, the noise level increases and the swing level of the voltage V1 of the first node NO1 decreases, thereby degrading a signal to noise ratio (SNR) and making it difficult to receive data at high speed.